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newViterbi217
- 基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误-IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct
Enc_With_Punc---2011-11-28-v3.0
- Viterbi 译码打孔和去打孔代码, ,VERILOG 代码，自己写的，包含时钟打孔，-Viterbi Decoder With Puncture and Depuncture， Verilog Code，clock puncture ,
viterbideoderupdated
- Viterbi decoder source code is in verilog with CRCv-Viterbi decoder source code is in verilog with CRCv
viterbi_decoder_axi4s_latest.tar
- viterbi解码电路，verilog实现，可以综合有使用价值-viterbi decoding circuit, verilog achieve, you can have the use of integrated value
Viterbi_algorithm_VeeRen
- Viterbi algorithm using Verilog
VITERBI_DECODER
- Verilog语言描述的应用于TD-SCDMA中的viterbi译码器rate_1-2_Viterbi_decoder-Applied in TD-SCDMA Verilog language descr iption of the viterbi decoder rate_1-2_Viterbi_decoder
src_vtb
- 用verilog实现的维特比译码电路，可以实现维特比译码-With verilog realize Viterbi decoding circuit, Viterbi decoding can be achieved
8398489
- 一个完整的viterbi(2,1,7)编码程序,使用的是Verilog语言()
MSJE362
- verilog实现卷积码的译码,viterbi算法()
eyye
- 一个完整的viterbi(2,1,7)编码程序,使用的是Verilog语言()